Notes on Digital Design

Notes on Digital Design

Verilog

There are two types of numbers, sized and unsized. Sized numbers are represented by size'base-format number. Unsized numbers are written without a size specification, but possibly with a base format. Sized numbers are always positive. The number of bits in an unsized number is implementation-dependent but must be at least 32. Literals with high bit x or z are extended with x or z. _ is allowed in a literal except as the first character.

Data types: nets, registers, vectors, integer, real, time. Vectors can be declared [high:low] or [low:high]. The number on the left is always the most significant bit. Values of type time are at least 64 bits. $time gets the current simulation time.

Arrays can have type reg, vector reg, integer or time. Multi-dimensional arrays are not supported. An array of reg and a vector reg are not the same. Memories are arrays of registers.

When a real is assigned to an integer, it is rounded to the nearest integer.

Strings can be stored in registers. Each character takes up 8 bits. Concatenation can be used on strings. $sformat

parameters

Concatenation can be used on the right-hand side of continuous assignment statements.

Behavioral Modeling

always and initial are structured statements that represent a concurrent activity. An initial block executes once at time 0. always block starts at time 0 and executes in a loop. If a statement is prefixed by #delay, its execution is delayed by delay units after the current execution time.

The right hand side of an assignment can be one of: a reg (or vector reg), integer, real, time, bit select, part select, or a concatenation of any of the above. There are two kinds of assignment: blocking and nonblocking. Blocking assignments are written with = and evaluate the right-hand side and immediately assign the left-hand side.

Non-blocking assignments are written with <= and the right-hand side is evaluated and the assignment executes at the end of the time step in which it is scheduled.

There are two kinds of timing controls: delay based and event based. There are three kinds of delay-based controls on assignments: regular, intra-assignment and zero delay. Event-based controls are specified with @. An event is a change on the value of a register or net. There are four types of event-based timing control: regular, named, OR, and level-sensitive. Level-sensitive timing control is written using the keyword wait.

case statement. The case value is compared to the alternatives in the order they are written. The comparison is done using case equality (===).

RESUME 7.6 Loops

Primitives

TODO: d-flipflop, t-flipflop